az12010 multiply by 16, 32 phase - locked loop clock generator 1630 s. stapley dr., suite 127 ? mesa, arizona 85204 ? usa ? (480) 962-5881 ? fax (480) 890-2541 www.azmicrotek.com arizona microtek, inc. features ? differential inputs/outputs for external voltage controlled saw oscillator ? optional internal crystal oscillator driver ? internal edge-matching phase/frequency detector ? internal charge-pump/integrator amplifier ? rf bipolar design for low phase noise ? available in a 3x3 mm mlp package description the az12010 contains all of the functional elements n ecessary to implement a phas e-locked loop for clock multiplication at frequencies up to 800 mhz. a fixed 32 times multiplication allows the use of low cost crystals or a low frequency reference signal. the output can be divided by two for 16 times net multiplication. the vcso is differentially or single-ended driven using the chip cml saw outputs. the dynamic properties of the pll are under the control of the user through selection of the desired external components. package availability package part no. marking notes mlp 16 (3x3) AZ12010AL az12010a 1,2 mlp 16 (3x3) rohs compliant / lead (pb) free AZ12010AL+ az12010a+ 1,2 mlp 16 (3x3) az12010bl az12010b 1,2 mlp 16 (3x3) rohs compliant / lead (pb) free az12010bl+ az12010b+ 1,2 die az12010xp n/a 3 1 add r1 at end of part number for 7 inch (1k parts), r2 for 13 inch (2.5k parts) tape & reel. 2 date code format: ?yy? for year followed by ?ww? for week. 3 waffle pack
az12010 november 2006 * rev - 5 www.azmicrotek.com 2 3x3 mlp 16 package azm12010a: cppol pulled high azm12010b: cppol pulled low
az12010 november 2006 * rev - 5 www.azmicrotek.com 3 die map pad center locations signal name x coordinate ( ) y coordinate ( ) sawin -522.0 372.3 sawin -522.0 220.3 test -522.0 68.3 enable -522.0 -83.7 v ee -522.0 -235.7 refin -522.0 -387.7 refout -365.0 -515.8 cpout -213.0 -515.8 cpref -61.0 -515.8 intref 91.0 -515.8 intsum 243.0 -515.8 v ee 395.0 -515.8 intout 552.0 -387.7 cppol 552.0 -235.7 v bb 552.0 -83.7 v eep 552.0 68.3 q 552.0 220.3 q 552.0 372.3 v cc 395.0 509.9 v cc 243.0 509.9 sawout 91.0 509.9 sawout -61.0 509.9 div_sel -219.0 509.9 v ee -377.0 509.9
az12010 november 2006 * rev - 5 www.azmicrotek.com 4 az12010 functional pin/pad descriptions name functional description logic level refin reference frequency input this pin/pad includes an on-chip 470 pull down resistor to v bb . the input from the reference circuit should be ac coupled. refout reference frequency output this pin is an inverted and amplified version of the signal on the refin pin. the gain from refin to refout is approximately 20. if v eep is connected to v ee , a 4 ma on-chip current source is provided for the output. refout is not available on the packaged versions (az12010a, az12010b). pecl cpref charge pump reference output the pin/pad voltage is nominally 1.2 volts below v cc . cpout charge pump output the charge pump output voltage is v cpref 0.3v during a phase correction pulse. when there is no correction pulse the output goes high impedance. cppol charge pump polarity when this pin/pad is pulled high the pll operates with a vcso circuit exhibiting negative pulling slope (the vcso frequency goes down when the control voltage goes up). when this pin/pad is pulled low (azm12010b) the pll operates with a vcso circuit exhibiting positive pulling slope (the vcso frequency goes up when the control voltage goes up). if the pin/pad is left open (azm12010a), an internal pullup resistor selects negative pulling slope mode. lvcmos lvttl intref integrator reference input this pin/pad should be connected to cpref through a bias curren t cancellation network intsum integrator summing junction this pin/pad is the summing junction for the integrator amplifier intout integrator output sawin sawin saw amplifier inputs if only one input is used (single-ended vcso), the unused input should be bypassed with a capacitor to v bb . sawout sawout saw amplifier outputs these are open collector outputs for driving the vcso device. operating at nominally 9 ma, external pullup resistors must be connected between these pins/pads and v cc . if only one output is used, the other output should be connected to v cc through a 50 ? resistor. cml (analog) enable pll output enable the q and q outputs are enabled when this pin/pad is pulled high. when this pin/pad is low, the q output is high, and the q output is low. if the pin/pad is left open, an internal pullup resistor enables the outputs. lvcmos lvttl div_sel divide select when this pin/pad is high, the q and q outputs are divided by one from the saw device. when it is low, the q and q outputs are divided by two from the saw device. if the pin/pad is left open, an internal pullup resistor selects the divide by one mode. lvcmos lvttl q q clock output these pin/pads are the main clock output. when enable is low, the outputs are disabled with q high and q low. pecl v bb reference voltage output this pin/pad is used to bias the refin signal. it must be bypassed externally to the v ee pins/pads with a 0.01 f capacitor. v eep refout current source if v eep is connected to v ee , a 4 ma on-chip current source is provided for the refout output. v eep is not available on the packaged versions (az12010a, az12010b). v cc positive supply +3.0 to +3.6 v v ee negative supply ground
az12010 november 2006 * rev - 5 www.azmicrotek.com 5 absolute maximum ratings are those values beyond which device life may be impaired. symbol characteristic rating unit v cc power supply (v ee = gnd) 0 to +6.0 vdc v i input voltage (v ee = gnd) 0 to +6.0 vdc i out pecl output current ? continuous ? surge 50 100 ma t a operating temperature range -40 to +85 c t stg storage temperature range -65 to +150 c az12010 dc characteristics (v cc = +3.0 to +3.6 v, v ee = gnd) -40 c 0 c 25 c 85 c symbol characteristic min max min max min typ max min max unit v bb reference voltage v cc -1.38 v cc -1.26 v cc -1.38 v cc -1.26 v cc -1.38 v cc -1.31 v cc -1.26 v cc -1.38 v cc -1.26 v r ref refin pull-down resistor to v bb 470 r saw sawin, sawin pull- down resistor to v bb 10k v hctl high level integrator output v cc -1.0 v cc -1.0 v cc -1.0 v cc -1.0 v v lctl low level integrator output 0.5 0.5 0.5 0.5 v v oh output high voltage 1 q, q v cc -1085 v cc -880 v cc -1025 v cc -880 v cc -1025 v cc -955 v cc -880 v cc -1025 v cc -880 mv v oh output high voltage 2 sawout, sawout v cc -10 v cc v cc -10 v cc v cc -10 v cc v cc -10 v cc mv v ol output low voltage 1 q, q v cc -1830 v cc -1555 v cc -1810 v cc -1620 v cc -1810 v cc -1705 v cc -1620 v cc -1810 v cc -1620 mv v ol output low voltage 2 sawout, sawout v cc -349 v cc -481 v cc -365 v cc -516 v cc -392 v cc -449 v cc -557 v cc -465 v cc -661 mv v ih input high voltage, lvcmos/lvttl en, div_sel 2.2 v cc 2.2 v cc 2.2 v cc 2.2 v cc v v il input low voltage, lvcmos/lvttl en, div_sel 0.0 0.8 0.0 0.8 0.0 0.8 0.0 0.8 v i cc (i ee ) power supply current 65 65 45 54 65 65 ma 1. load is 50 to v cc -2v 2. load is 50 to v cc az 12010 ac characteristics (v cc = +3.0 to +3.6 v, v ee = gnd) -40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit a pd phase detector gain 20.3 radians/v f vco external vsco frequency 800 800 800 mhz t r / t f output rise & fall times (20% - 80%) q, q 120 ps a v saw amplifier and driver gain at 622.08 mhz 1 18 24.5 28 15.5 21 24.5 13.5 19 22.5 db 1. single ended input and output, driven from 50 backmatched source, load 50 to v cc .
az12010 november 2006 * rev - 5 www.azmicrotek.com 6 loop filter design the combination of the phase detector, amplifier, vco and divider form a second-order phase-locked loop. proper selection of the loop components is importa nt to obtain stable , low jitter operation. the loop bandwidth (or natural frequency, n ) and damping factor ( ) are the two major driving forces that define the loop?s response to a disturbance. the value of is typically 0.7 to ensure the fastest step response consistent with no ringing. however in many oscillator application may be 3 or higher to provide further phase noise reduction. n is chosen as a compromise between settling time, vco jitter and reference feedthrough. these values can be computed by the following equations: 1 1 vco n k k n = 2 2 n = 1 1 1 c r = 1 2 2 c r = = k phase detector gain (20.3 radians/v) = vco k vco gain (radians/sec/volt) = n frequency divisor value (32) the component definitions are shown in th e figure below. r3 should be equal to r1 to minimize integrator offsets. charge pump intref intsum intout cpref cpout integrator r2 c1 r1 r3 external vcso control voltage figure 1 charge pump and integrator
az12010 november 2006 * rev - 5 www.azmicrotek.com 7 application circuit a typical application circuit is shown in figure 2. f sawin phase/ freq detect charge pump outpt drvr input rcvr mux refin v bb refout 4ma 470 sawin vbb intsum intout cpout integrator v ee v eep pll output /2 /16 enable div_sel sawout sawout enable cont q q saw drive saw rcvr 2 x 10k cpref cppol intref r2 c1 r1 r3 vcc ground c2 0.01 f saw resonator w/ matching & tuning network r5 r4 c3 0.01 f v cc figure 2. typical application, always enabled and divide by one for output
az12010 november 2006 * rev - 5 www.azmicrotek.com 8 millimeters dim min max a 0.80 1.00 a1 0.00 0.05 a3 0.25 ref b 0.18 0.30 d 3.90 4.10 d2 2.65 2.95 e 3.90 4.10 e2 2.65 2.95 e 0.50 bsc l 0.35 0.45 aaa 0.25 bbb 0.10 ccc 0.10 notes 1. dimensioning and tolerancing conform to asme t14-1994. 2. the terminal #1 and pad numbering convention shall conform to jesd 95-1 spp-012. 3. dimension b applies to metallized pad and is measured between 0.25 and 0.30mm from pad tip. 4. coplanarity applies to the exposed pad as well as the terminals. package diagram mlp 16 millimeters dim min max a 0.80 1.10 a1 0.00 0.05 a3 0.25 ref b 0.225 0.275 d 2.90 3.10 d2 1.65 1.95 e 2.90 3.10 e2 1.65 1.95 e 0.50 bsc l 0.35 0.45 aaa 0.25 bbb 0.10 ccc 0.10 notes 1. dimensioning and tolerancing conform to asme t14-1994. 2. the terminal #1 and pad numbering convention shall conform to jesd 95-1 spp-012. 3. dimension b applies to metallized pad and is measured between 0.25 and 0.30mm from pad tip. 4. coplanarity applies to the exposed pad as well as the terminals.
az12010 november 2006 * rev - 5 www.azmicrotek.com 9 arizona microtek, inc. reserves the right to change circuitry a nd specifications at any time without prior notice. arizona mic rotek, inc. makes no warranty, representation or guarant ee regarding the suitability of its products for any particular purpose, nor does a rizona microtek, inc. assume any liability arising out of the applica tion or use of any product or ci rcuit and specifically disclaims any and all liability, including without limitation special, consequential or inci dental damages. arizona microtek, inc. does not convey a ny license rights nor the rights of others. arizona microtek, inc. products are not designed, intended or authorized for use as component s in systems intended to support or sustain life, or for any other applicati on in which the failure of the arizona microtek, inc. product co uld create a situation where personal injury or death may occur. should buye r purchase or use arizona microtek, inc. products for any such unintended or unauthorized application, buyer shall indemnify a nd hold arizona microtek, inc. a nd its officers, employees, subs idiaries, affiliates, and distributor s harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising ou t of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim al leges that arizona microtek, inc. was negligent regarding the design or manufacture of the part.
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